開發產品

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普思半導體目前共擁有17份半導體領域之專利

13

發明

4

新型

產品開發方向

先進封裝疊對改善 - 背面複刻對準鍵

Thru backside laser marking duplicates alignment marks from the front to the backside to improve bonding alignment accuracy, reducing the global limitation from 50nm to 35nm. This enhances bonding process precision and improves bonding yield (related to 2.5D/4D/CoWoS/HBM technologies).

To control the local temperature of the wafer/substrate to improve bonding alignment accuracy. This enhances bonding process precision and improves bonding yield (related to 2.5D/4D/CoWoS/HBM technologies).

To control the local temperature of the wafer/substrate to improve bonding alignment accuracy. This enhances bonding process precision, enables structural inspection, and improves bonding yield (related to 2.5D/4D/CoWoS/HBM technologies).

EPE(edge placement error) improvement for advanced node Logic(2nm-14nm)/Memory product (DRAM, Flash), yield improvement

NZO(Non-Zero-Offset) improvement for advanced node, major in Memory product (DRAM, Flash), yield improvement

XCDX purge with pressure cycling to speed up mask VOC dilution